Semiconductor device with interconnection structure for reducing stress migration

ABSTRACT

The semiconductor device of the present invention includes a first interconnection, a via-plug that is connected to the first interconnection, and a second interconnection that is formed as a single unit with the via-plug. The cross-sectional shape of the via-plug is such that the plug sidewall angle, which indicates the angle of the via-plug sidewall with respect to the surface of the first interconnection, is a positive angle; and moreover, at least two points exist between the base and the top of the via-plug on at least one sidewall of the two sidewalls of the cross-sectional shape of the via-plug at which the plug sidewall angle attains a maximum value. Since shapes that would give rise to the occurrence of concentrations of stress are not formed in the via-plug sidewalls, metal is more effectively embedded in the via-hole, and the incidence of voids is prevented.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device havinginterconnections and a via-plug for connecting the interconnectionstogether, and to a fabrication method for such a semiconductor device.

[0003] 2. Description of the Related Art

[0004] Among semiconductor devices such as memory and logic devices arethose that conventionally include an interconnection structure in whichinterconnections are connected together by via-plugs. FIG. 1 is asectional view showing an example of the configuration of asemiconductor device of the prior art. As shown in FIG. 1, thesemiconductor device is a configuration that includes: interconnection120 on lower dielectric film 110 that is formed on a semiconductorsubstrate (not shown); via-plug 230 that is connected to interconnection120; and interconnection 140 that is connected to via-plug 230. Via-plug230 and interconnection 140 are formed as a single unit.

[0005] The effect of the shape of via-plugs upon stress migration insuch an interconnection structure has previously been documented (T.Oshima et al., “Suppression of stress-induced voiding in copperinterconnects,” IEDM (2002)).

[0006] However, although the effect of the shape of via-plugs uponstress migration has been touched upon in the above-describedliterature, nothing has been disclosed regarding methods of solving thisproblem, and it is unclear how stress migration can be reduced.

SUMMARY OF THE INVENTION

[0007] It is an object of the present invention to provide asemiconductor device having an interconnection structure for reducingstress migration and a method of fabricating such a semiconductordevice.

[0008] The semiconductor device of the present invention includes: afirst interconnection; a via-plug that connects to the firstinterconnection; and a second interconnection that is formed as a unitwith the via-plug; wherein a cross-sectional shape of the via-plug is aconfiguration in which a plug sidewall angle, which indicates an angleof the via-plug sidewall with respect to the surface of the firstinterconnection, is a positive angle; and moreover, that has at leasttwo points between a base and a top of the via-plug on at least one ofthe two sidewalls of the cross-sectional shape of the via-plug at whichthe plug sidewall angle attains a maximum value.

[0009] More specifically, the plug sidewall angle is an angle formedbetween: a line that joins an arbitrary point of a sidewall of thevia-plug and a point of intersection of a line that passes through thatarbitrary point and that is parallel to the first interconnection and acentral axis of the via-plug; and a line that joins that arbitrary pointand a point of intersection between a tangent line at that arbitrarypoint and the central axis. In addition, regarding the plug sidewallangle, an angle of depression from a line that is parallel to thesurface of the first interconnection is a positive angle, and an angleof elevation from a line that is parallel to the first interconnectionis a negative angle.

[0010] In the present invention, the plug sidewall angle in thecross-sectional shape of the via-plug does not become a negative angle,and as a result, shape that would cause stress to concentrate are notformed in the via-plug sidewalls of the via-plug cross-sectional shape.In addition, because a minimum value exists between the two maximumvalues for the plug sidewall angle, an inclination of the sidewallchanges such that a via-hole diameter increases midway from the via-plugbase to the top, and the essential aspect ratio of the via-hole istherefore smaller than for a simple tapered shape.

[0011] In addition, if the plug sidewall angle is a positive angle atany point of the via-plug sidewall, a sidewall shape will be formed inwhich the plug sidewall angles are positive angles for all of thevia-plug sidewalls. As a result, a shape that would cause stress toconcentrate is not formed on any of the via-plug sidewalls.

[0012] In addition, when the plug sidewall angle is less than or equalto 90°, the via-hole sidewalls will have a shape that is amenable toburying metal in the via-hole interior.

[0013] Still further, if the plug sidewall angle is a continuous valuebetween the maximum values, the via-hole sidewalls will have a gentleshape between the points on the sidewalls at which the plug sidewallangles attain maximum values even if the plug sidewall angle has amaximum value that approaches 90°. As a result, a shape that would giverise to concentrations of stress will not be formed even when an angleof 90° is approached or between differing inclinations.

[0014] In addition, the amenability of the via-hole interiors to fillingwith metal is further improved when the plug sidewall angle is less than90° between the via-plug base and the points on via-plug sidewalls atwhich the plug sidewall angle becomes a minimum value between maximumvalues.

[0015] Moreover, the amenability of the via-hole interiors to fillingwith metal is further improved if a metal diffusion barrier film isincluded on the first interconnection, and if the plug sidewall angle atthe position of the side surface of the metal diffusion barrier film isless than 90°.

[0016] Accordingly, shapes that would bring about a concentration ofstress are not formed on the via-plug sidewalls in the semiconductordevice of the present invention, and as a result, the via-hole interioris more amenable to filling with metal, and the occurrence of voids canbe prevented. Moreover, stress migration is reduced and the reliabilityof the interconnections is improved.

[0017] The above and other objects, features, and advantages of thepresent invention will become apparent from the following descriptionwith reference to the accompanying drawings, which illustrate examplesof the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1 is a sectional view showing an example of the configurationof a semiconductor device of the prior art;

[0019]FIG. 2A is a sectional view showing an example of theconfiguration of a semiconductor device of the present invention;

[0020]FIG. 2B is a plan view showing an example of the configuration ofthe semiconductor device of the present invention;

[0021]FIG. 3 is a schematic view showing the sectional shape of avia-plug;

[0022]FIG. 4 is a graph showing the via-plug sidewall shape in thesemiconductor device shown in FIG. 2A;

[0023]FIG. 5 is a graph showing the via-plug sidewall shape of thesemiconductor device shown in FIG. 1;

[0024]FIG. 6 is a graph showing the dependency of stress migrationfailure rate upon the interconnection width of the upper metal;

[0025]FIGS. 7A to 7N are sectional views showing the method offabricating the semiconductor device of the present invention;

[0026]FIG. 8A is a sectional view showing the configuration of thesemiconductor device of the second working example; and

[0027]FIG. 8B is a plan view showing the configuration of thesemiconductor device of the second working example.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIRST WORKING EXAMPLE

[0028] As shown in FIG. 2A, the semiconductor device is a configurationthat includes: interconnection 120 on lower dielectric film 110 that isformed on a semiconductor substrate (not shown); via-plug 130 that isconnected to interconnection 120; and interconnection 140 that isconnected to via-plug 130. Via-plug 130 and interconnection 140 areformed as a single unit. Interconnection 120, via-plug 130, andinterconnection 140 each include the conductive material copper (Cu) anda barrier metal film for preventing diffusion of the copper.

[0029] Intralayer dielectric film 112 for insulating interconnection 120from interconnections that are formed on the same level is formed onlower dielectric film 110. The upper surface of interconnection 120 iscovered by Cap-SiCN film 152, which forms a metal diffusion preventionfilm for preventing the diffusion of copper at points other than thepoints of connection with via-plug 130. Interconnection 140 is formed inintralayer dielectric film 116, and interlayer dielectric film 114 isformed between interconnection 120 and interconnection 140. Cap-SiCNfilm 156 is formed as a metal diffusion prevention film oninterconnection 140.

[0030] Stopper-SiC film 150 is formed to act as an etching stopper filmbetween lower dielectric film 110 and intralayer dielectric film 112.Stopper-SiC film 154 is formed as an etching stopper film betweeninterlayer dielectric film 114 and intralayer dielectric film 116.

[0031] Interlayer dielectric film 114 is a silicon oxide film.Intralayer dielectric film 112 and intralayer dielectric film 116 areladder oxide films having a ladder-type hydrogenated siloxane structure.In the following explanation, ladder oxide films are referred to as“L-Ox (a registered trademark of NEC Electronics Corporation) films”.

[0032] Semiconductor elements such as transistors, resistors, capacitorsare formed on the semiconductor substrate, but the structure of thesemiconductor elements is similar to that of semiconductor elements ofthe prior art, and detailed explanation of this structure is thereforehere omitted.

[0033] The following explanation regards the angles of the sidewalls ofthe via-plug in the sectional shape of the semiconductor device that isshown in FIG. 2A.

[0034]FIG. 3 is a schematic view showing the sectional shape of avia-plug. In FIG. 3, via-plug 130 is connected to interconnection 120.Lt is a line that is tangent to an arbitrary point 330 of the via-plugsidewall, and Lp is a line at point 330 that is parallel to the surfaceof interconnection 120. Further, Lc is the central axis of the via-plug.Point 340 is the point of intersection between line Lp at point 330 andcentral axis Lc, and point 350 is the point of intersection betweentangent line Lt at point 330 and central axis Lc. Plug sidewall angle θis the angle formed between the line formed by joining point 340 andpoint 330 and the line formed by joining point 330 and point 350. Inaddition, the angle of depression from line Lp for this plug sidewallangle is a positive angle, and the angle of elevation from line Lp is anegative angle.

[0035] In the semiconductor device that is shown in FIG. 2A, theabove-described plug sidewall angle is a positive angle greater than 0°and less than or equal to 90° from the top of the via-plug at the baseof interconnection 140 to the base of the via-plug. This point isexplained hereinbelow using a graph that shows the shape of the via-plugsidewall.

[0036]FIG. 4 is a graph showing the shape of the via-plug sidewall ofthe semiconductor device shown in FIG. 2A. The vertical axis shows thevalue of the plug sidewall angle, and the horizontal axis shows thedistance from the top of the via-plug when tracing the sidewall of thevia-plug shown in FIG. 2A. Point 300 on the horizontal axis shows thetop of the via-plug, and point 320 shows the base of the via-plug. Point310 shows an intermediate point between point 300 and point 320.

[0037] As shown in FIG. 4, the plug sidewall angle increases graduallyfrom the angle at point 300, and decreases gradually upon exceeding amaximum value. After attaining a minimum value at point 310, the angleagain gradually increases to reach a maximum value, whereupon the angledecreases up to point 320. The plug sidewall angle is never a negativeangle, and sidewall of the via-plug is therefore formed in a smoothshape. In addition, as shown in the graph, the plug sidewall angle hastwo maximum values, is a continuous value between the two maximumvalues, and has no discontinuous points. The plug sidewall angle variesgradually before and after point 310 and does not change radically evenat point 310 where the plug sidewall angle reaches a minimum value.Although the sidewall angle does not attain 90° in this graph, pointswith a 90° are permissible.

[0038] As with the above-described plug sidewall shape, the plugsidewall angle does not become a negative angle, and there areconsequently no areas that would give rise to a concentration of stress.As a result, stress migration in the via-plug is reduced. In the shapeof the via-plug sidewall, moreover, the plug sidewall angle has at leasttwo maximum values, and further, has a minimum value between thesemaximum values. At the point of this minimum value, the inclination ofthe sidewalls changes such that the diameter of the via-hole(hereinbelow referred to as “via-hole diameter”) increases midway fromthe base of the via-plug to the top of the via-plug, and the essentialaspect ratio of the via-hole therefore is smaller than that of a simpletapered shape. As a result, the via-hole is more amenable to fillingwhen the via-hole is filled with copper. As a result of these factors,stress migration inside the via-plug is reduced and an interconnectionhaving high reliability is obtained.

[0039]FIG. 2B is a plan view showing the pattern of interconnection 140and via-plug 130. Point 300 of FIG. 2B shows the top of the via-plug,and point 320 shows the base of the via-plug. As shown in FIG. 2B, theshape of the sidewall from via-plug base 320 to via-plug top 300 that isshown in FIG. 2A is formed on all of the via-plug sidewalls.

[0040] The following explanation regards the shape of theabove-described via-plug sidewalls for a case in the prior art. The filmconfiguration of the semiconductor device of the prior art is similar tothat of the semiconductor device of the present invention shown in FIG.2A, and a detailed explanation of this configuration is thereforeomitted.

[0041] As shown in FIG. 1, a protuberance is formed at the positionshown by point 410 on the sidewalls of via-plug 230. This shape is nextexplained using a graph that shows the plug sidewall angle.

[0042]FIG. 5 is a graph showing the shape of the via-plug sidewall ofthe semiconductor device shown in FIG. 1. The vertical axis shows thevalue of the plug sidewall angle, and the horizontal axis shows thedistance from the top of the via-plug when tracing the via-plug sidewallthat is shown in FIG. 1. Point 400 on the horizontal axis shows thevia-plug top, and point 420 shows the via-plug base. Point 410 shows anintermediate point between point 400 and point 420.

[0043] As shown in FIG. 5, the plug sidewall angle first increases frompoint 400 that indicates the via-plug top, but after attaining a maximumvalue, decreases and then becomes a negative angle at point 410. Frompoint 410, the plug sidewall angle again increases, and after continuingas a substantially fixed value, drops precipitously to point 420 (O). Aprotuberance is thus formed at the position at which the plug sidewallangle becomes a negative angle. Stress is consequently focused at theprotuberance in the via-hole, and stress migration tends to occur in thevia-plug. In addition, the via-hole is not amenable to filling withcopper, and voids tend to occur in the via-plug. The formation of voidsdecreases the product yield, and further, leads to the breakdown ofconnections between interconnection 120 and interconnection 140 as voidsgrow in the course of extended use of the semiconductor device.

[0044] The following explanation regards an appraisal of stressmigration for the interconnection structures of the semiconductor deviceshown in FIG. 2A and the semiconductor device shown in FIG. 1. In thisexplanation, Sample A is a sample produced according to theinterconnection structure of the semiconductor device shown in FIG. 2A,and Sample B is a sample produced according to the interconnectionstructure of the semiconductor device shown in FIG. 1. In addition,interconnection 120 is referred to as “lower-metal,” and interconnection140 is referred to as “upper-metal.”

[0045] In this appraisal, a via-chain TEG (Test Element Group) was usedin which the connections of the lower-metal, via-plug and upper-metalwere formed by repeating a prescribed number of times. In addition,several conditions were set regarding the interconnection width of theupper-metal based on a range of 0.2-10 μm, where the interconnectionwidth is the direction that is perpendicular to the longitudinaldirection of the interconnections in the planar pattern of theinterconnections. The interconnection width of the lower-metal wasfixed.

[0046] Experimentation was carried out as follows: Samples A and SamplesB were each fabricated, a plurality of via-chain TEGs being formedaccording to the above-described conditions. Samples A and Samples Bwere next kept at a temperature of 150° C. for 168 hours, followingwhich the via-chain TEGs were subjected to the application of voltageand then checked to determine whether current flowed. Via-chain TEGs inwhich current did not flow at this time were determined to be defectivedue to stress migration.

[0047] The above-described conditions on the interconnection width ofthe upper-metal in this appraisal were established because stressmigration failures tend to occur with increase in the interconnectionwidth of the upper-metal.

[0048] Regarding the reasons for this phenomenon, heat treatment in theprocess of fabricating a semiconductor device causes residual tensilestress in interconnections. Stress migration is the phenomenon by whichmetal atoms move through the interconnections or via-plugs to relievethis tensile stress. Voids are generated in a via-plug to relieve thestress of the upper-metal. When the interconnection width of theupper-metal is small, the stress is relieved even though the volume ofthe voids is small. In contrast, when the interconnection width isgreat, the alleviation of stress is inadequate when the volume of thevoids is small, and voids of greater volume are therefore necessary forrelieving stress. However, the occurrence of voids having large volumein the via-plug leads to the connection failure of the via-plug.

[0049] Regarding the results of the appraisal of stress migration, FIG.6 is a graph showing the dependence of the stress migration failure rateupon the interconnection width of the upper-metal. The horizontal axisshows the interconnection width of the upper-metal, and the verticalaxis shows the stress migration failure rate (hereinbelow referred to assimply the “failure rate”). The value of the failure rate for Sample Ais plotted by blank triangles, while the failure rate for Sample B isplotted using solid dots.

[0050] As shown in FIG. 6, the failure rate was 0 for Sample A despiteincrease of the interconnection width of the upper-metal from 0.2 μm to10 μm. In contrast, failures occurred in Sample B when theinterconnection width of the upper-metal became greater than 1 μm, andthe failure rate continued to increase as the interconnection widthincreased. Based on the reasons described hereinabove, it is believedthat when the interconnection width of the upper-metal exceeded 1 μm inSample B, voids occurred that promoted breaks in the connections of thevia-plug.

[0051] Based on the results shown in FIG. 6, it can be seen that thestress migration characteristic of Sample A is far superior to that ofSample B. As the reason for this difference, points that would causeconcentrations of stress do not occur in Sample A because the plugsidewall angle never becomes a negative angle, while protuberances areformed in Sample B at points in which the plug sidewall angle becomes anegative angle.

[0052] The following explanation regards a method of fabricating thesemiconductor device that is shown in FIG. 2A. The explanation hereregards a dual damascene method in which via-plug 130 andinterconnection 140 are formed as a single unit.

[0053]FIGS. 7A to 7N are sectional views showing the fabrication methodof the semiconductor device of the present invention. Semiconductorelements such as transistors and resistors are formed on a semiconductorsubstrate that is not shown in the figure, but because the configurationof the semiconductor elements is similar to that of the prior art,explanation of the method of forming these elements is here omitted.

[0054] As shown in FIG. 7A, after forming the above-describedsemiconductor elements, a silicon oxide film is formed as lowerdielectric film 110 having a film thickness of 400-700 nm by a plasmaCVD (Chemical Vapor Deposition) method.

[0055] Next, Stopper-SiC film 150 having a thickness of 50-70 nm isformed, an L-Ox film having a thickness of 400-700 nm is formed asintralayer dielectric film 112, and a resist film is then applied overthese films. Trench openings are next formed in the resist film by meansof a known lithographic process. The resist film is used as a mask toremove Stopper-SiC film 150 and intralayer dielectric film 112,following which the resist film is removed.

[0056] After forming a barrier metal film 122 (FIG. 7B), a copper seedlayer is formed, following which copper 124 is formed on the copper seedlayer by means of an electroplating method (FIG. 7C).

[0057] As shown in FIG. 7D, copper 124 is next polished by means of aCMP (Chemical and Mechanical Polishing) method until the upper surfaceof intralayer dielectric film 112 is exposed, whereby interconnection120 is formed.

[0058] Next, as shown in FIG. 7E, Cap-SiCN film 152 is formed to athickness of 50-70 nm, and a silicon oxide film is formed to a thicknessof 400-700 nm as interlayer dielectric film 114. Stopper-SiC film 154 isthen formed to a film thickness of 50-70 nm, and an L-Ox film is formedto a film thickness of 400-700 nm as intralayer dielectric film 116.

[0059] Interlayer dielectric film 114, Stopper-SiC film 154, andintralayer dielectric film 116 are next removed by a known lithographicprocess and etching process until prescribed positions of the uppersurface of Cap-SiCN film 152 are exposed as shown in FIG. 7F, wherebyopening 134 for forming the via-hole is formed.

[0060] Next, anti-reflective coating (hereinbelow abbreviated as “ARC”)160 is applied in order that the resist film will not be exposed tolight reflected by interconnection 120 in the subsequent lithographyprocess (FIG. 7G). At this time, ARC 160 is applied such that theposition of the upper surface of ARC 160 inside opening 134 that wasshown in FIG. 7F is below the lower surface of Stopper-SiC film 154. Inthe following explanation, the opening in which ARC 160 is buried inopening 134 is referred to as opening 135. ARC 160 is an organic film inwhich polyvinyl phenol or polymethyl methacrylate is added to a baseresin of polyimide or novolac.

[0061] As shown in FIG. 7H, after applying resist film 162 by means of aknown lithographic process, trench opening 148 for forminginterconnection 140 is formed in resist film 162 (FIG. 71).

[0062] Using resist film 162 as a mask, plasma etching is carried outfrom trench opening 148 using a mixed gas of CF₄ and Ar in which the gasmixture ratio of CF₄: Ar equals 1:5 and the pressure is 13.3-53.2 Pa(100-400 mTorr).

[0063] By means of this plasma etching, not only is intralayerdielectric film 116 of trench opening 148 eliminated until the uppersurface of Stopper-SiC film 154 is exposed, but the sidewalls ofinterlayer dielectric film 114 of opening 135 are also removed such thatthe diameter of the opening is greater at the top than at the base ofthe opening (FIG. 7J). At this time, interlayer dielectric film 114 isnot etched as far as a position lower than the upper surface of ARC 160.ARC 160 below opening 135 serves as a protective film for preventingelimination of the via-hole sidewalls by etching.

[0064] Next, as shown in FIG. 7K, resist film 162 and ARC 160 areremoved by performing an O₂ plasma ashing process and an organicstripping agent process. Plasma etching is next carried out from thetrench opening that has been formed in intralayer dielectric film 116using a mixed gas of CHF₃, O₂, and Ar. This plasma etching eliminatesStopper-SiC film 154 and Cap-SiCN film 152 that have been exposed onupper surfaces and forms via-hole 137 and a trench opening forinterconnection 140 (FIG. 7L). At this time, the plug sidewall angle forthe sidewalls of via-hole 137 at Cap-SiCN film 152 may be less thanpositive 900.

[0065] Barrier metal film 142 and copper seed layer are next formed insuccession, and copper 144 is embedded by an electroplating method invia-hole 137 and in the trench opening for interconnection 140 (FIG.7M). At this time, the via-hole diameter is greater toward the via-holetop than at the via-hole base, and the step coverage of the copper seedlayer and barrier metal film 142 that are formed in the via-hole istherefore excellent and the embedding of copper 144 is improved.

[0066] Copper 144 is next polished by means of a CMP method until theupper surface of intralayer dielectric film 116 is exposed to forminterconnection 140, following which Cap-SiCN film 156 is formed tocover the upper surface of interconnection 140 (FIG. 7N). Thesemiconductor device shown in FIG. 2A is thus completed. After formingthe structure shown in FIG. 2A, an interlayer dielectric film may alsobe additionally formed to form an interconnection on the upper layer.

[0067] The above-described fabrication method produces a shape in whichthe sidewalls of the via-hole drop monotonously from the via-hole toptoward the via-hole base, and as a result, a shape is not produced inwhich the sidewall angles upward from a horizontal direction atmidpoints of the sidewalls that drop toward the via-hole base. Further,the inclination of the sidewalls changes such that the via-hole diameterincreases with progress along the via-hole sidewall from the via-holebase toward the via-hole top.

[0068] The smoother via-hole sidewalls, and moreover, smaller essentialaspect ratio of the via-hole in the semiconductor device of theabove-described working example brings about an improvement in the stepcoverage when forming the barrier metal film, resulting in excellentembedding of copper and the production of a via-plug and interconnectionin which voids do not occur. It is further believed that this type ofconfiguration tends to eliminate concentrations of stress inside thevia-plug and can thus eliminate the starting points of void nucleation.Interconnections can thus be obtained that feature reduced stressmigration in the via-plugs and high reliability. In particular, thesuppression of concentrations of stress eliminates the occurrence ofstress migration failures even when stress increases as a result of theincreased width of interconnection 140. Still further, by making theplug sidewall angle α positive angle for any points of the via-plugsidewalls, the sidewall shape from the via-plug base to the via-plug topis formed for all of the via-plug sidewalls. As a result, the formationof shapes that would lead to the occurrence of stress concentration isprevented on all of the via-plug sidewalls.

[0069] Still further, making the plug sidewall angle at the point ofCap-SiCN film 152 that is shown in FIG. 2A less than 90° provides astill greater improvement in the embedding of metal in the via-holeinterior and allows better prevention of the occurrence of voids.

[0070] Regarding the etching process that was shown in FIG. 7J, althougha case was shown in which a mixed gas of CF₄ and Ar was used as theetching gas such that the etching rate of ARC 160 was greater than thatof interlayer dielectric film 114, a mixed gas of C₄F₈ and Ar may alsobe used such that the etching rate of ARC 160 is less than that ofinterlayer dielectric film 114. C₂F₆ gas may also be used in place ofCF₄.

SECOND WORKING EXAMPLE

[0071] The present working example is a semiconductor device that isprovided with a via-plug in which only a portion of the via-plug has thesidewall shape of the via-plug in the first working example.

[0072] The following explanation regards the semiconductor device of thepresent working example. Identical reference numerals are applied tocomponents that are identical to those of the first working example anddetailed explanation of such components is here omitted. In addition,the fabrication for this working example is identical to that of thefirst working example and explanation of this method is therefore hereomitted.

[0073] As shown in FIG. 8A, the semiconductor device of this workingexample is a configuration that includes: interconnection 120; via-plug136 that is connected to interconnection 120; and interconnection 146that is formed as a single unit with via-plug 136. Regarding thesectional shape of the via-plug sidewall that is shown in FIG. 8A, theleft side of the figure is the same shape as in the first workingexample, but on the right side of the figure, the plug sidewall angle isuniform from the upper surface of interconnection 146 to the base of thevia-plug. The plug sidewall angle of the sidewall on the right side ofthe figure may be within the range over 0° to a positive 900.

[0074]FIG. 8B is a plan view showing the pattern of interconnection 146and via-plug 136. Point 500 in FIG. 8B shows the via-plug top and point520 shows the via-plug base. As shown in FIG. 8B, the pattern ofinterconnection 146 extends to the left of the figure from via-plug 136.As a result, the via-plug sidewall shape such as the shape shown in thefirst working example is not formed on the right-side portion of thesidewalls.

[0075] If the same shape as in the first working example is provided inthe via-plug sidewalls at least from the via-plug top to the via-plugbase as in the present working example, the same effects can be obtainedas were obtained in the first working example.

[0076] Although the metal copper was used as the material of theabove-described interconnections and via-plug in the above-describedfirst working example and second working example, the metal may be analloy that contains copper, or may be another metal such as aluminum ortungsten.

[0077] Further, although L-Ox film was used in intralayer dielectricfilms 112 and 116 as a low-dielectric-constant dielectric film having alower dielectric constant than a silicon oxide film, the presentinvention is not limited to the use of L-Ox film. Thelow-dielectric-constant dielectric film may be an inorganic dielectricfilm such as either a SiOF film or a silicon oxide film containingcarbon (SiOC film). Alternatively, the low-dielectric-constantdielectric film may be an organic dielectric film such as either asilicon oxide film containing a methyl group or a high-polymer film.Still further, intralayer dielectric films 112 and 116 may also belaminated films that include these low-dielectric-constant dielectricfilms. Although a case was shown in which interlayer dielectric film 114was a silicon oxide film, interlayer dielectric film 114 may be a filmthat contains a low-dielectric-constant dielectric film. The use of alow-dielectric-constant dielectric film in intralayer dielectric films112 and 116 and interlayer dielectric film 114 reduces the capacitancebetween interconnections.

[0078] Further, the etching stopper film is not limited to a SiC filmand may be a SiCN film or a silicon nitride film having high etchingselectivity with intralayer dielectric films. Still further, the metaldiffusion prevention film is not limited to a SiCN film, and may also bea dielectric film such as a SiC film or a silicon nitride film thatserves the purpose of preventing diffusion of metal.

[0079] While preferred embodiments of the present invention have beendescribed using specific terms, such description is for illustrativepurposes only, and it is to be understood that changes and variationsmay be made without departing from the spirit or scope of the followingclaims.

What is claimed is:
 1. A semiconductor device having a firstinterconnection, a via-plug that is connected to said firstinterconnection, and a second interconnection that is formed as a singleunit with said via-plug; wherein: regarding a plug sidewall angle in across-sectional shape of said via-plug, said plug sidewall angle beingan angle formed between: a line that joins an arbitrary point of asidewall of said via-plug and a point of intersection between a linethat passes through said arbitrary point and that is parallel to asurface of said first interconnection and a central axis of saidvia-plug, and a line that joins said arbitrary point and a point ofintersection between a tangent line at said arbitrary point and saidcentral axis, an angle of depression from a line that is parallel to thesurface of said first interconnection is a positive angle, and an angleof elevation from a line that is parallel to the surface of said firstinterconnection is a negative angle; and in the cross-sectional shape ofsaid via-plug, said plug sidewall angle is a positive angle; and thereare at least two points between a base and a top of said via-plug on atleast one of two sidewalls of said via-plug cross-sectional shape atwhich said plug sidewall angle attains a maximum value.
 2. Thesemiconductor device according to claim 1, wherein said plug sidewallangle at arbitrary points of the sidewalls of said via-plug is apositive angle.
 3. The semiconductor device according to claim 1,wherein said plug sidewall angle is equal to or less than
 900. 4. Thesemiconductor device according to claim 1, wherein said plug sidewallangle is a continuous value between said two points of maximum value. 5.The semiconductor device according to claim 1, wherein said plugsidewall angle at an arbitrary point, said arbitrary point being betweena point on the sidewall of said via-plug at which said plug sidewallangle becomes a minimum value between said two maximum values and thebase of said via-plug, is less than 90°.
 6. The semiconductor deviceaccording to claim 1, comprising a metal diffusion prevention film thatis formed on said first interconnection; wherein said plug sidewallangle at arbitrary points of the sidewall of said via-plug at a portionof said metal diffusion prevention film is an angle less than 90°.
 7. Afabrication method of a semiconductor device, said semiconductor devicehaving a first interconnection, a via-plug that is connected to saidfirst interconnection, and a second interconnection that is connected tosaid via-plug; said fabrication method comprising the steps of:successively forming on said first interconnection: a first metaldiffusion prevention film, an interlayer dielectric film, an etchingstopper film, and an intralayer dielectric film; using a lithographicprocess and an etching process to form a first opening in a prescribedopening pattern in said interlayer dielectric film, said etching stopperfilm, and said intralayer dielectric film; applying an antireflectivecoating for preventing a reflection of light by said firstinterconnection, and forming a second opening in said first opening inwhich said antireflective coating is buried such that a position of anupper surface of said antireflective coating is lower than a lowersurface of said etching stopper film; forming a resist film having aprescribed pattern of trench openings in said intralayer dielectricfilm; performing etching with said resist film as a mask to form atrench opening in said intralayer dielectric film, and forming sidewallsof said interlayer dielectric film of said second opening such that adiameter of said second opening is progressively larger from a bottomtoward a top of said second opening; removing said resist film and saidantireflective coating; etching from the trench opening that has beenformed in said intralayer dielectric film to remove said etching stopperfilm and said first metal diffusion prevention film that have beenexposed on upper surfaces and forming a via-hole that includes saidsecond opening and the trench opening of said second interconnection;and embedding a metal in said via-hole and the trench opening of saidsecond interconnection to form said via-plug and said secondinterconnection, and then forming a second metal diffusion preventionfilm.
 8. The fabrication method of a semiconductor device according toclaim 7, wherein: regarding a plug sidewall angle in a cross-sectionalshape of said via-hole following formation of said via-hole, said plugsidewall angle being an angle formed between: a line that joins anarbitrary point of a sidewall of said via-hole and a point ofintersection of a line that passes through said arbitrary point and thatis parallel to a surface of said first interconnection and a centralaxis of said via-hole, and a line that joins said arbitrary point and apoint of intersection between a tangent line at said arbitrary point andsaid central axis, an angle of depression from a line that is parallelto the surface of said first interconnection is a positive angle, and anangle of elevation from a line that is parallel to the surface of saidfirst interconnection is a negative angle; and in the cross-sectionalshape of said via-hole, said plug sidewall angle is a positive angle;and at least two points exist between a base and a top of said via-holeon at least one of two sidewalls of said via-hole cross-sectional shapeat which said plug sidewall angle attains a maximum value.